Here's all the first euler problems I've done.
And here's everything.

MyHDL
 Feb 1, 2016 MyHDL: Multiples of 3 and 5
 Apr 5, 2016 MyHDL: Even Fibonacci numbers
 Apr 19, 2016 MyHDL: Largest Prime Factor

VHDL
 Jan 20, 2016 VHDL: Multiples of 3 and 5
 Feb 1, 2016 VHDL: Even Fibonacci numbers

Verilog
 Mar 27, 2017 Verilog: Multiples of 3 and 5

euler1
 Jan 20, 2016 VHDL: Multiples of 3 and 5
 Feb 1, 2016 MyHDL: Multiples of 3 and 5
 Mar 27, 2017 Verilog: Multiples of 3 and 5

euler2
 Feb 1, 2016 VHDL: Even Fibonacci numbers
 Apr 5, 2016 MyHDL: Even Fibonacci numbers

euler3
 Apr 19, 2016 MyHDL: Largest Prime Factor
As part of my verilog exploration, I'm also going to look try to just use the open source tools available for the verilog design chain. Project IceStorm is a Verilog to bitstream flow for Lattice iCE40 FPGAs. For simulation I'm going to use Icarus Verilog. Like so many open source tools, documentation could be better. I've not had a good experience in the past using open source tools for FPGA design, but hopefully these tools work out well.